COSC 065 Hardware Systems

Fall 2006



Lectures:
MWF 12:00PM - 12:50PM Cudahy 412
Office Hours:
Course instructor
  Prof. Dennis Brylow   Mon 3:00PM - 4:00PM Cudahy 380
Mon 7:00PM - 8:00PM Cudahy 380
Wed 3:00PM - 4:00PM Cudahy 380
Fri 11:00AM - 12:00PM Cudahy 380

Textbook:
Essentials of Computer Architecture. Douglas Comer. Prentice-Hall
Readings will be regularly assigned from the textbook.    Lectures will assume that students have already read the assigned chapters.   In addition, some of the written homework problems may be assigned out of the book.   Some of these problems also make excellent exam questions.

Course Outcomes:
Upon completing this course, students will be able to:
  • Understand the principles underlying computer hardware systems, and appreciate how these principles shape software;
  • Define and describe the purpose of major components in modern computer hardware, and understand how these components work together to accomplish computing;
  • Read and write assembly languages for two common computer processors, and employ these assembly languages to solve programming problems.

  • Grading Policy:
    Homework 60%
    Pop Quizzes 5%
    Exam #1 10%
    Exam #2 10%
    Exam #3 15%
  • Students must pass BOTH the exam portion of the grade AND and homework assignment portion of the grade to pass the course overall.
  • Assignments are to be completed individually, except when specifically noted otherwise. You may discuss course topics with your collegues, but written work and programmed code is not to be shared.
  • Academic dishonesty (claiming another person's work as your own) will not be tolerated. Infractions will result in immediate failure of the course, and referral to the Dean's office.
  • If you are not certain what constitutes fair play and what will be considered academic dishonesty, please ask the instructor.
  • Schedule:
    Week Topics Readings Demos Assignments
    01 Introduction, Digital Logic Ch 1
    02 Digital Logic Ch 2 #1 Digital Logic
    03 Combinational and Sequential Logic #2 Sequential Logic
    04 Data Representation Ch 3
    05 Processors, Pipelines Ch 4 #3 Representation
    06 Instruction Sets, RISC Exam #1
    07 Assembly Languages Ch 5 Adding.S #4 Basic PPC Assembly
    08 Addressing Modes Ch 6 Midterm Break
    09 Activation Records Ch 7, 8 getInt.S #5 Medium PPC Assembly
    10 CISC Ch 9, 10 fib.S Exam #2
    11 Memory and Storage Ch 11 #6 Activation Records
    12 Virtual Memory Ch 12 #7 Large PPC Assembly 13 Caches Ch 13 Thanksgiving Break
    14 I/O Ch 14, 15 Intel x86 #8 Basic Intel
    15 Buses, Interrupts Ch 16 #9 Large Intel
    Final Exam #3
    The instructor reserves the right to adjust this schedule as necessary.

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    [Revised 2006 Oct 22 21:40 DWB]